1. Field of the Invention
The present invention relates to a decoding apparatus and decoding method. The present invention particularly relates to speedup of entropy coding/decoding processing as a compression scheme used to encode a moving image or still image. The present invention is particularly suitable for arithmetic decoding processing as an entropy decoding method.
2. Description of the Related Art
Recently, the H.264 (ITU-T Rec.H.264|ISO/IEC 14496-10 AVC) coding scheme has been standardized in joint video team (JVT). The H.264 handles image information as digital data, like JPEG known as a still image coding scheme and MPEG-2 or MPEG-4 (version 2) known as a moving image coding scheme. Particularly in the moving image coding scheme, compression using hybrid coding is executed to reduce redundant information between frames (in the temporal direction) and redundant information of pixels in a frame (in the spatial direction), aiming at efficient information transmission and storage. This hybrid coding uses entropy coding together with orthogonal transform such as discrete cosine transform and motion-compensation. Entropy coding is a technique of executing variable length coding using uneven distribution of information.
As entropy coding used in the H.264, Context-based Adaptive Variable Length Coding (CAVLC) using Huffman coding or Context-Adaptive Binary Arithmetic Coding (CABAC) using arithmetic coding is defined in accordance with the profile. CAVLC is selected in a baseline profile which includes coding tools with low process complexity for a communication application. CABAC is selected in a main profile or high profile that places focus on the coding efficiency.
As is generally known, arithmetic coding implemented by software or hardware is difficult to speed up as compared to variable length coding such as Huffman coding or Golomb coding. FIG. 10 is a flowchart of CABAC decoding processing described in, for example, the H.264 recommendation (ITU-T Rec.H.264|ISO/IEC 14496-10 AVC). This decoding processing is hard to speed up because a process loop S213 of CABACParsing(SE) processing in FIG. 10 is executed for every bit (symbol). FIGS. 11 and 12 respectively show arithmetic decoding processing and re-normalization processing disclosed in “H.264 Reference Software Joint Model ver9.0”. Note that DecodeBin(ctxIdx) (S208 in FIG. 10) includes DecodeDecision(ctxIdx) as arithmetic coding and DecodeBypass as fixed length encoding. The simple DecodeBypass processing is omitted here. The processes shown in FIGS. 11 and 12 are DecodeDecision(ctxIdx). Using the value of a state variable obtained by the arithmetic decoding processing shown in FIG. 11, the CABAC re-normalization processing shown in FIG. 12 updates the value of the state variable itself and also obtains the number of bits to be removed from the top of received coded data. That is, before the current target symbol undergoes all processes shown in FIGS. 11 and 12, decoding of the next symbol cannot start.
The CABAC scheme performs encoding/decoding in units of symbols generated by binarizing a syntax element of a coding target in advance. More specifically, the CABAC scheme generates a plurality of symbols from one syntax element, unlike Huffman coding in which one syntax element corresponds to one symbol. For this reason, the CABAC requires a much longer process time for coding/decoding processing than the CAVLC using Huffman coding.
Japanese Patent Laid-Open Nos. 11-103257 and 2005-130099 disclose techniques of implementing an arithmetic decoding apparatus by hardware. These techniques smoothly arithmetically encode symbol data in correspondence with each clock by executing a pipeline operation of address generation in a context memory for holding a state and calculations in arithmetic coding.
Along with the recent rapid increase in the resolution represented by high-resolution images, a demand for coding and decoding apparatuses capable of high-speed processing has arisen. In hybrid coding represented by H.264, in particular, a factor that decides the processing speed of an entire decoding apparatus is speedup of an entropy decoding apparatus.
However, even when the technique disclosed in Japanese Patent Laid-Open No. 11-103257 or 2005-130099 is used, only one symbol is decodable in one cycle at maximum. It is difficult to execute the decoding processing at a higher speed.
For example, even if two arithmetic decoding units operate in parallel to increase the processing speed, decoding of the second symbol cannot start unless decoding of the first symbol completely finishes. It is therefore difficult to execute the two arithmetic decoding units in one cycle.